The effect of limited I/O bandwidth on the computation speed of VLSI arrays is studied. For simple operations such as matrix multiplication, computation time can be reduced significantly by selecting an appropriate configuration for interfacing and controlling the array. Reconfiguration techniques are used to restructure a pattern analysis array so that it can carry out the successive phases of required computations without the data leaving the array. Computation time is reduced, since with the reconfigurable array the limited I/O bandwidth affects only the first and last phases of the necessary computations. The array can be used to generate covariance matrices, compute matrix inversion, and calculate linear and quadratic discriminant functions for pattern recognition. The image-processing array is designed for both spatial domain and frequency domain operations. Because of the large number of pixels in an image, it is likely that the array will be partitioned and implemented on multiple chips. The effect of limited interchip I/O bandwidth on computation speed is examined.
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