Vlsi Array Design Under Constraint of Limited I/O Bandwidth

Philip S. Liu, Tzay Y. Young

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


Under the constraint of limited I/O bandwidth of the host system or the computing array, three configurations for the interfacing and controlling of a multiplication array to achieve optimal performance under different adverse situations are examined: multiplexing loading, processor row loading, and processor column group loading. A properly chosen configuration can significantly reduce computing time. For the inversion of covariance matrix which involves several distinct functional computations, a reconfigurable mesh connected square array is used to minimize the adverse effect of limited I/O bandwidth. Compared with a pipeline of functional computing arrays which also compute the inverse, the reconfigurable array takes much less time to accomplish the same task. A new array structure for L-U decomposition is proposed and compared with previous approaches.

Original languageEnglish (US)
Pages (from-to)1160-1170
Number of pages11
JournalIEEE Transactions on Computers
Issue number12
StatePublished - Dec 1983


  • Design constraints
  • VLSI architecture
  • VLSI implementation
  • image processing
  • matrix inversion array
  • multiplication array
  • performance analysis
  • reconfigurable VLSI array
  • signal processing

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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