PIPELINED DATA BROADCASTING IN VLSI ARRAY DESIGN.

Philip S. Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Feasibility of data broadcasting within a VLSI computing array depends on a number of factors such as interprocessor I/O bandwidth, hardware complexity, array throughput, vertical integration and external I/O bandwidth. The design and analysis of a systolic matrix multiplier is used to relate these factors.

Original languageEnglish
Title of host publicationConference Proceedings - Annual Phoenix Conference
Place of PublicationNew York, NY, USA
PublisherIEEE
Pages115-120
Number of pages6
ISBN (Print)0818606142
StatePublished - Dec 1 1985

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Broadcasting
Bandwidth
Throughput
Hardware

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Liu, P. S. (1985). PIPELINED DATA BROADCASTING IN VLSI ARRAY DESIGN. In Conference Proceedings - Annual Phoenix Conference (pp. 115-120). New York, NY, USA: IEEE.

PIPELINED DATA BROADCASTING IN VLSI ARRAY DESIGN. / Liu, Philip S.

Conference Proceedings - Annual Phoenix Conference. New York, NY, USA : IEEE, 1985. p. 115-120.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, PS 1985, PIPELINED DATA BROADCASTING IN VLSI ARRAY DESIGN. in Conference Proceedings - Annual Phoenix Conference. IEEE, New York, NY, USA, pp. 115-120.
Liu PS. PIPELINED DATA BROADCASTING IN VLSI ARRAY DESIGN. In Conference Proceedings - Annual Phoenix Conference. New York, NY, USA: IEEE. 1985. p. 115-120
Liu, Philip S. / PIPELINED DATA BROADCASTING IN VLSI ARRAY DESIGN. Conference Proceedings - Annual Phoenix Conference. New York, NY, USA : IEEE, 1985. pp. 115-120
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