Feasibility of data broadcasting within a VLSI computing array depends on a number of factors such as interprocessor I/O bandwidth, hardware complexity, array throughput, vertical integration and external I/O bandwidth. The design and analysis of a systolic matrix multiplier is used to relate these factors.
|Original language||English (US)|
|Title of host publication||Conference Proceedings - Annual Phoenix Conference|
|Number of pages||6|
|State||Published - Dec 1 1985|
|Name||Conference Proceedings - Annual Phoenix Conference|
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