For a large problem size and limited silicon area, the problem can be partitioned into smaller subproblems which can be individually computed by an optimal processor array of the same size. With the same amount of silicon area and external I/O bandwidth, a second array can also be designed with smaller PEs (processing elements), resulting in an array of many more PEs. Each PE will take a longer time to produce a result. However, a large problem may now be handled by the second array without partitioning the problem. Using data broadcasting, the computation time of the second array can equal that of the first array. Architecture and implementation tradeoffs between the two approaches are examined.
|Title of host publication||Unknown Host Publication Title|
|Editors||Malcolm L. Heimer, Donald J. Larnard, Miami Florida Int Univ|
|Place of Publication||New York, NY, USA|
|Number of pages||5|
|State||Published - Dec 1 1987|
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