Abstract
For a large problem size and limited silicon area, the problem can be partitioned into smaller subproblems which can be individually computed by an optimal processor array of the same size. With the same amount of silicon area and external I/O bandwidth, a second array can also be designed with smaller PEs (processing elements), resulting in an array of many more PEs. Each PE will take a longer time to produce a result. However, a large problem may now be handled by the second array without partitioning the problem. Using data broadcasting, the computation time of the second array can equal that of the first array. Architecture and implementation tradeoffs between the two approaches are examined.
| Original language | English |
|---|---|
| Title of host publication | Unknown Host Publication Title |
| Editors | Malcolm L. Heimer, Donald J. Larnard, Miami Florida Int Univ |
| Place of Publication | New York, NY, USA |
| Publisher | IEEE |
| Pages | 212-216 |
| Number of pages | 5 |
| State | Published - Dec 1 1987 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
OPTIMAL AND BROADCASTING PROCESSOR ARRAYS. / Liu, Philip S.
Unknown Host Publication Title. ed. / Malcolm L. Heimer; Donald J. Larnard; Miami Florida Int Univ. New York, NY, USA : IEEE, 1987. p. 212-216.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - OPTIMAL AND BROADCASTING PROCESSOR ARRAYS.
AU - Liu, Philip S.
PY - 1987/12/1
Y1 - 1987/12/1
N2 - For a large problem size and limited silicon area, the problem can be partitioned into smaller subproblems which can be individually computed by an optimal processor array of the same size. With the same amount of silicon area and external I/O bandwidth, a second array can also be designed with smaller PEs (processing elements), resulting in an array of many more PEs. Each PE will take a longer time to produce a result. However, a large problem may now be handled by the second array without partitioning the problem. Using data broadcasting, the computation time of the second array can equal that of the first array. Architecture and implementation tradeoffs between the two approaches are examined.
AB - For a large problem size and limited silicon area, the problem can be partitioned into smaller subproblems which can be individually computed by an optimal processor array of the same size. With the same amount of silicon area and external I/O bandwidth, a second array can also be designed with smaller PEs (processing elements), resulting in an array of many more PEs. Each PE will take a longer time to produce a result. However, a large problem may now be handled by the second array without partitioning the problem. Using data broadcasting, the computation time of the second array can equal that of the first array. Architecture and implementation tradeoffs between the two approaches are examined.
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UR - http://www.scopus.com/inward/citedby.url?scp=0023594805&partnerID=8YFLogxK
M3 - Conference contribution
SP - 212
EP - 216
BT - Unknown Host Publication Title
A2 - Heimer, Malcolm L.
A2 - Larnard, Donald J.
A2 - Florida Int Univ, Miami
PB - IEEE
CY - New York, NY, USA
ER -