ESTIMATING THE SPEEDUP IN PARALLEL PARSING.

Dilip Sarkar, Narsingh Deo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A method for estimating the speedup for asynchronous bottom-up parallel parsing is presented. Two models for bottom-up parallel parsing are proposed, and the speedup for each of them is estimated using the technique developed here. The speedup obtained for one model is very close to the simulation result already available in literature. The second model shows a greater speedup than the first.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
EditorsKai Hwang, Steven M. Jacobs, Earl E. Swartzlander
PublisherIEEE
Pages157-163
Number of pages7
ISBN (Print)0818607246
StatePublished - Dec 1 1986

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Sarkar, D., & Deo, N. (1986). ESTIMATING THE SPEEDUP IN PARALLEL PARSING. In K. Hwang, S. M. Jacobs, & E. E. Swartzlander (Eds.), Proceedings of the International Conference on Parallel Processing (pp. 157-163). (Proceedings of the International Conference on Parallel Processing). IEEE.