Estimating the Speedup in Parallel Parsing

Dilip Sarkar, Narsingh Deo

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A method for estimating the speedup for asynchronous bottom-up parallel parsing has been presented. Two models for bottom-up parallel parsing are proposed, and the speedup for each of the two models is estimated using the technique developed here. The speedup obtained for one model is very close to the simulation result already available in literature. The second model shows a greater speedup than the first.

Original languageEnglish (US)
Pages (from-to)677-683
Number of pages7
JournalIEEE Transactions on Software Engineering
Volume16
Issue number7
DOIs
StatePublished - Jan 1 1990

Keywords

  • Compilers
  • parallelism
  • parsing

ASJC Scopus subject areas

  • Software

Cite this

Estimating the Speedup in Parallel Parsing. / Sarkar, Dilip; Deo, Narsingh.

In: IEEE Transactions on Software Engineering, Vol. 16, No. 7, 01.01.1990, p. 677-683.

Research output: Contribution to journalArticle

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