### Abstract

The computational power of 2-D and 3-D processor arrays that contain a potentially large number of faults is analyzed. Both a random and a worst-case fault model are considered, and it is proved that in either scenario low-dimensional arrays are surprisingly fault tolerant. It is also shown how to route, sort, and perform systolic algorithms for problems such as matrix multiplication in optimal time on faulty arrays. In many cases, the running time is the same as if there were no faults in the array (up to constant factors). On the negative side, it is shown that any constant congestion embedding of an n × n fault-free array on an n × n array with Θ(n^{2}) random faults (or Θ(log n) worst-case faults) requires dilation Θ(log n). For 3-D arrays, knot theory is used to prove that the required dilation is Ω(√log n).

Original language | English (US) |
---|---|

Pages (from-to) | 285-296 |

Number of pages | 12 |

Journal | IEEE Transactions on Industry Applications |

Volume | 27 |

Issue number | 1 pt 1 |

State | Published - Jan 1991 |

Externally published | Yes |

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### ASJC Scopus subject areas

- Engineering (miscellaneous)
- Electrical and Electronic Engineering

### Cite this

*IEEE Transactions on Industry Applications*,

*27*(1 pt 1), 285-296.

**Asymptotically tight bounds for computing with faulty arrays of processors.** / Kaklamanis, C.; Karlin, A. R.; Leighton, F. T.; Milenkovic, Victor; Raghavan, P.; Rao, S.; Thomborson, C.; Tsantilas, A.

Research output: Contribution to journal › Article

*IEEE Transactions on Industry Applications*, vol. 27, no. 1 pt 1, pp. 285-296.

}

TY - JOUR

T1 - Asymptotically tight bounds for computing with faulty arrays of processors

AU - Kaklamanis, C.

AU - Karlin, A. R.

AU - Leighton, F. T.

AU - Milenkovic, Victor

AU - Raghavan, P.

AU - Rao, S.

AU - Thomborson, C.

AU - Tsantilas, A.

PY - 1991/1

Y1 - 1991/1

N2 - The computational power of 2-D and 3-D processor arrays that contain a potentially large number of faults is analyzed. Both a random and a worst-case fault model are considered, and it is proved that in either scenario low-dimensional arrays are surprisingly fault tolerant. It is also shown how to route, sort, and perform systolic algorithms for problems such as matrix multiplication in optimal time on faulty arrays. In many cases, the running time is the same as if there were no faults in the array (up to constant factors). On the negative side, it is shown that any constant congestion embedding of an n × n fault-free array on an n × n array with Θ(n2) random faults (or Θ(log n) worst-case faults) requires dilation Θ(log n). For 3-D arrays, knot theory is used to prove that the required dilation is Ω(√log n).

AB - The computational power of 2-D and 3-D processor arrays that contain a potentially large number of faults is analyzed. Both a random and a worst-case fault model are considered, and it is proved that in either scenario low-dimensional arrays are surprisingly fault tolerant. It is also shown how to route, sort, and perform systolic algorithms for problems such as matrix multiplication in optimal time on faulty arrays. In many cases, the running time is the same as if there were no faults in the array (up to constant factors). On the negative side, it is shown that any constant congestion embedding of an n × n fault-free array on an n × n array with Θ(n2) random faults (or Θ(log n) worst-case faults) requires dilation Θ(log n). For 3-D arrays, knot theory is used to prove that the required dilation is Ω(√log n).

UR - http://www.scopus.com/inward/record.url?scp=0025742359&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025742359&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0025742359

VL - 27

SP - 285

EP - 296

JO - IEEE Transactions on Industry Applications

JF - IEEE Transactions on Industry Applications

SN - 0093-9994

IS - 1 pt 1

ER -