## Abstract

The computational power of 2-D and 3-D processor arrays that contain a potentially large number of faults is analyzed. Both a random and a worst-case fault model are considered, and it is proved that in either scenario low-dimensional arrays are surprisingly fault tolerant. It is also shown how to route, sort, and perform systolic algorithms for problems such as matrix multiplication in optimal time on faulty arrays. In many cases, the running time is the same as if there were no faults in the array (up to constant factors). On the negative side, it is shown that any constant congestion embedding of an n × n fault-free array on an n × n array with Θ(n^{2}) random faults (or Θ(log n) worst-case faults) requires dilation Θ(log n). For 3-D arrays, knot theory is used to prove that the required dilation is Ω(√log n).

Original language | English (US) |
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Pages (from-to) | 285-296 |

Number of pages | 12 |

Journal | IEEE Transactions on Industry Applications |

Volume | 27 |

Issue number | 1 pt 1 |

State | Published - Jan 1 1991 |

Externally published | Yes |

Event | 1989 Industry Applications Society Annual Meeting - San Diego, CA, USA Duration: Oct 1 1989 → Oct 5 1989 |

## ASJC Scopus subject areas

- Control and Systems Engineering
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering