The presence of limit cycles that may arise in fixedpoint arithmetic implementation of a digital filter can significantly impair its performance. This paper presents an algorithm to determine the presence/absence of such limit cycles. For generality the filter is taken to be in its state-space formulation. The algorithm is applicable independent of filter order type of quantization nonlincarity and whether the accumulator is single or double length. It may be utilized to construct limit cycle free regions in filter coefficient space. Once a filter is determined to be limit cycle free a technique that provides a robustness region in coefficient space where all filters remain limit cycle free is also presented.
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering