Adjustable block size coherent caches

Czarek Dubnicki, Thomas J. LeBlanc

Research output: Chapter in Book/Report/Conference proceedingConference contribution

42 Scopus citations


Large cache blocks exploit processor and spatial locality, but may cause unnecessary cache invalidations due to false sharing. Small cache blocks can reduce the number of cache invalidations, but increase the number of bus or network transactions required to load data into the cache. A cache organization that dynamically adjusts the cache block size according to recently observed reference behavior is described. Cache blocks are split across cache lines when false sharing occurs, and merged back into a single cache line to exploit spatial locality. To evaluate this cache organization, a scalable multiprocessor with coherent caches is simulated, using a suite of memory reference traces to model program behavior. It is shown that for every fixed block size, some program suffers a 33% increase in the average waiting time per reference, and a factor of 2 increase in the average number of words transferred per reference, when compared with the performance of an adjustable block size cache. In the few cases where adjusting the block size does not provide superior performance, it comes within 7% of the best fixed block size alternative.

Original languageEnglish (US)
Title of host publicationConference Proceedings - Annual Symposium on Computer Architecture
PublisherPubl by IEEE
Number of pages11
ISBN (Print)0897915097, 9780897915090
StatePublished - 1992
Event19th International Symposium on Computer Architecture - Gold Coast, Aust
Duration: May 19 1992May 21 1992

Publication series

NameConference Proceedings - Annual Symposium on Computer Architecture


Other19th International Symposium on Computer Architecture
CityGold Coast, Aust

ASJC Scopus subject areas

  • Engineering(all)


Dive into the research topics of 'Adjustable block size coherent caches'. Together they form a unique fingerprint.

Cite this